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cha4220 - qgg ref. : dscha4220 - qgg - 5070 - 11 mar 15 1 / 16 specifications subject to change without notice united monolithic semiconductors s.a.s. bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 0.5 - 20ghz driver gaas monolithic micr owave ic description the cha4220 - qgg is a distributed driver amplifier that operat es between 0.5 and 20 ghz . it is designed for a wide range of a pplications, such as electronic warfare , x and ku point to point radio , and t est instrumentation. the circuit is manufa ctured using a 0.2 5m gate length power phemt process , with via holes through the substrat e, air bridges and optical gate lithography. the part is supplie d as 5x5 qfn package with input and output rf accesses matched to 50 ohms. main features main electrical characteristics tamb . = + 25c symbol parameter min typ max unit freq frequency range 0. 5 2 0 ghz gain linear gain 1 7 db nf noise figure 3 db pout output power @1db comp. 20 dbm 0 5 10 15 20 25 30 0 2 4 6 8 10 12 14 16 18 20 22 gain, nf / p1db, pout frequency (ghz) performance p1db (dbm) linear gain (db) psat (dbm) nf(db) ums a4220 yyww ?? ums a3667a yywwg ums a3667a yywwg ums a3688a yywwg ums a3667a yywwg ums a3667a yywwg ums a3688a yywwg ums a3667a yywwg ums a3667a yywwg ums a3688a yywwg ums a3667a yywwg ums a3667a yywwg ums a3688a yywwg ums a3667a yywwg ums a3667a yywwg ums a3688a yywwg ums a3667a yywwg ums a3667a yywwg ums a3688a yywwg ums a3667a yywwg ums a3667a yywwg ums a3688a yywwg ums a3667a yywwg ums a3667a yywwg ums a3688a yywwg
cha4220 - qgg 0.5 - 20ghz driver ref. : dscha4220 - qgg - 5070 - 11 mar 15 2 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: + 33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 electrical characteristics tamb . = + 25c , vg1 t o be set in order to have idq=12 0ma, vg2=1.5 v symbol parameter min typ max unit freq frequency range 0. 5 2 0 ghz gain linear gain 1 7 db nf noise figure 3 db irl input return loss 1 5 db orl output return loss 1 8 db p1db output power for 1db gain compression 20 db m psat saturated output power 2 3 dbm oip3 output third order intercept 28 dbm id q quiescent current on vd 12 0 ma vd supply voltage on vd 6 6.5 7 v id drain current @3db gain compression 1 40 ma the values ar e representative of typical test fixture measurements as defined on the ragraph typical bias conditions tamb .= +25c symbol pin parameter values unit v g 1 1 2 gate control1 for the amplifier - 0. 3 v v g 2 1 gate control2 for the amplifier 1. 5 v vd 19 drain voltage (see application circuit p10) 6.5 v the associated drain current with no rf input power is idq=12 0ma this typical bias is recommended in order to get the best compromise between output power, linearity and noise figure performance vs. temperature.
0.5 - 20ghz driver cha4220 - qgg ref. : dscha4220 - qgg - 5070 - 11 mar 15 3 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 absolute maximum ratings (1) tamb .= + 25c symbol parameter values unit vd drain bias voltage 8 v v idq drain bias current 1 7 0 ma vg1 gate bias voltage vg1 - 2 to 0 v vg2 gate bias voltage vg2 1 to 2 v pin maximum cw input power overdrive 1 7 dbm t a operating temperature range (chip backside) - 40 to 85 c tstg storage temperature range - 55 to +150 c (1) operation of this device above anyone of these parame ters may cause permanent damage: these maximum ratings parameters could not be cumulated . these are stress ratings only, and functional operation of the device at these conditions is not implied.
cha4220 - qgg 0.5 - 20ghz driver ref. : dscha4220 - qgg - 5070 - 11 mar 15 4 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: + 33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 device thermal performance all the figures given in this section are obtained assuming that the qfn device is cooled down only by conduction through the package thermal pad (no convection mode considered). the temperature is monitored at the package back - side interface (tcase) as shown below. the system max imum temperature must be adjusted in order to guarantee that tcase remains below the maximum value specified in the next table. so, the system pcb must be designed to comply with this requirement. a derating must be applied on the dissipated power if the tcase temperature cannot be maintained below the maximum temperature specified (see the curve pdiss. max) in order to guarantee the nominal device life time (mttf). the provided thermal information in the next chart is f or the worst biasing point: idq=11 0 ma and vd=7 v, without rf drive @tcase=85c.
0.5 - 20ghz driver cha4220 - qgg ref. : dscha4220 - qgg - 5070 - 11 mar 15 5 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 typical board measurements tamb .= +25c , vd = 6.5 v, vg1 set in order to get id q =12 0 ma , vg2=1.5 v linear gain versus frequency (ghz) and vd (v) broadband linear gain and return losses versus frequency 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 2 4 6 8 10 12 14 16 18 20 22 linear gain (db) frequency (ghz) linear gain (db) vs. vd (v) vd=6v vd=6.5v vd=7v - 30 - 25 - 20 - 15 - 10 - 5 0 5 10 15 20 0 5 10 15 20 25 30 35 40 linear gain, return losses (db) frequency (ghz) linear gain, return losses (db) s11(db) s22(db) s21(db)
cha4220 - qgg 0.5 - 20ghz driver ref. : dscha4220 - qgg - 5070 - 11 mar 15 6 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: + 33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 typical board measurements vd = 6.5 v, v g1 set in order to get idq =12 0 ma @ tamb=+25c with vg2=1.5 v vg1 and vg2 remain constant versus temperature (tamb .= +25c , +85c, - 40c ) linear gain v s t emperature noise figure vs temperature 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 18 20 22 linear gain (db) frequency (ghz) linear gain vs. temperature - 40 c 25 c +85 c 0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20 22 noise figure (db) frequency (ghz) noise figure vs. temperature - 40 c 25 c +85 c
0.5 - 20ghz driver cha4220 - qgg ref. : dscha4220 - qgg - 5070 - 11 mar 15 7 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 typical board measurements tamb .= +25c , vd = 6. 5 v, v g1 set in order to get idq =120 ma , vg2=1.5 v pout (dbm) v s . compression level drain current consumption (ma) vs. compression level 10 12 14 16 18 20 22 24 26 28 30 0 2 4 6 8 10 12 14 16 18 20 22 pout (dbm) frequency (ghz) pout vs. frequency and compression level @1db gain compression @2db gain compression @4db gain compression 0 20 40 60 80 100 120 140 160 180 200 0 2 4 6 8 10 12 14 16 18 20 22 id (ma) frequency (ghz) id (ma) vs. frequency and compression level @1db gain compression @2db gain compression @4db gain compression
cha4220 - qgg 0.5 - 20ghz driver ref. : dscha4220 - qgg - 5070 - 11 mar 15 8 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: + 33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 typical board measurements vd =6.5 v, v g1 set in order to get idq =120 ma @ tamb=+25c with vg2=1.5v vg1 and vg2 remain constant versus temperature (tamb .= +25c , +85c, - 40c ) output ip3 (dbm) vs temperature tamb.= +25c, vd =6.5 v, v g1 set in order to get idq =120 ma , vg2=1.5v main performance versus pin (dbm) @ freq=12 ghz 0 5 10 15 20 25 30 35 40 0 2 4 6 8 10 12 14 16 18 20 22 oip3 (dbm) frequency (ghz) output ip3 vs. temperature - 40 c 25 c +85 c 60 100 140 180 220 260 0 5 10 15 20 25 - 10 - 8 - 6 - 4 - 2 0 2 4 6 8 10 12 14 16 drain current (ma) pout (dbm), gain (db) pin (dbm) pout (dbm), gain (db), id (ma) @12 ghz gain pout id
0.5 - 20ghz driver cha4220 - qgg ref. : dscha4220 - qgg - 5070 - 11 mar 15 9 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 package outline : 28 leads 5x5 qfn (1) matt e tin, lead free (green) 1 - vg 2 11 - gnd (2) 21 - nc units : mm 2 - nc 12 - vg1 22 - nc from the standard : jedec mo - 220 3 - nc 13 - acg4 23 - nc (vhh d) 4 - rf in 14 - acg3 24 - nc 29 - gnd 5 - gnd (2) 15 - nc 25 - nc 6 - nc 16 - nc 26 - acg2 7 - nc 17 - nc 27 - acg1 8 - nc 18 - gnd (2) 28 - nc 9 - nc 19 - rf out +vd 10 - nc 20 - nc (1) the package outline drawing included to this data - sheet is given for indication. refer to the application note an0017 ( http://www.ums - gaas.com ) for exact package dimensions. (2) it is strongly recommended to ground all pins marked gnd through the pcb board.
cha4220 - qgg 0.5 - 20ghz driver ref. : dscha4220 - qgg - 5070 - 11 mar 15 10 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: + 33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 a pplication circuit : note: external components are requested in order to use the part properly: on rf input access a dc block is requested, on rf output access a bias tee is requested. depending on the board, additional capacitors such as 1f may be added on vg1 or vg2 access if necessary , for better low frequency decoupling. smaller capacitors than 470nf could be use i f the p art is not use in low frequency range (< 1 ghz): 10nf. vg1 26 vg2 rfin rfout + vd 1 4 19 12 100pf 10nf 1nf 470nf 100pf 10nf cha4220 - qgg 27 13 14 1nf 470nf external dc block preferred external bias tee is preferred vd
0.5 - 20ghz driver cha4220 - qgg ref. : dscha4220 - qgg - 5070 - 11 mar 15 11 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 pin description: pin symbol description 5,18, 29 (exposed pad) gnd must be grounded properly, internal connections to ground are made 2,3,6,7,8,9,10 ,15, 16,17,20,21,22,23,24,25, 28 nc no internal connections 4 rf in rf input , dc coupled to vg1 1 2 vg1 gate voltage, bias network required 1 vg2 gate voltage bias network required 19 rf out + vd rf output + vd bias (see application circuit) 13 agc4 low frequency termination 4 on vg1 14 agc3 low frequency termination 3 on vg1 26 agc2 low frequency termination 2 on vd 27 agc1 low frequency termination 1 on vd ums rec ommends also to ground pin 2, 3, 6, 7, 11, 15, 16, 17 , 20, 21 (see proposed footprint p14).
cha4220 - qgg 0.5 - 20ghz driver ref. : dscha4220 - qgg - 5070 - 11 mar 15 12 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: + 33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 proposed evaluation board compatible with the proposed footprint on page p14 . top dielectric material is rogers 4003 / 8mils or equivalent substrate . decoupling capacitors at first leve l are 100pf on vg1 and vg2. decoupl i ng capacitors at second level are 10nf on vg1 and vg2. additional capacitors such as 1f may also be added on each vg accesses . low frequency terminations are closed on 1nf and 470nf (proposal)
0.5 - 20ghz driver cha4220 - qgg ref. : dscha4220 - qgg - 5070 - 11 mar 15 13 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 device operation device power up instructions: 1) ground the device . 2) set vg1 to - 1.5 v . 3) set vd to 6. 5v (nominal value for vd) . 4) set vg2 to 1.5 v (nominal value for vg2 ) . 5) set vg1 in the range of - 0.3v for having idq=12 0ma . 6) apply rf input power and adjust vg2 to obtain desired gain . device power down instructions: 1) turn rf power supply off . 2) set vg1 to - 1.5 v in order to get idq=0ma . 3) set vg2 to 0v . 4) set vd to 0v. 5) set vg1 to 0v. dc schematic vd = 6. 5 v , vg1= - 0.3v, vg2=1.5v, idq=12 0 ma
cha4220 - qgg 0.5 - 20ghz driver ref. : dscha4220 - qgg - 5070 - 11 mar 15 14 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: + 33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 package footprint and definition of the measurements planes the reference planes used for the provided measurements are symmetrical from the symmetrical axis of the package (see drawing beside). the input and output refe rence planes are located at 3.65 mm offset (input wise and output wise respectively) from this axis. from the edge of the qfn, the referenc e planes are 1.15mm apart. package information parameter value package body material rohs - compliant low stress injection molded plastic lead finish 100% matte tin ( sn ) msl rating msl3 3.65 mm 3.65 mm
0.5 - 20ghz driver cha4220 - qgg ref. : dscha4220 - qgg - 5070 - 11 mar 15 15 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 note
cha4220 - qgg 0.5 - 20ghz driver ref. : dscha4220 - qgg - 5070 - 11 mar 15 16 / 16 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: + 33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 recommended package footprint refer to the application note an0017 available at http://www.ums - gaas.com for package foot print recommendations. smd mounting procedure for the mounting process standard techniques involving solder paste and a suitable reflow process can be used. for further details, see application note an0017. recommended environmental management ums products are compliant with the regulation in particular with the directives rohs n2011/65 and reach n1907/2006. more environmental data are available in the application note an0019 also available at http://www.u ms - gaas.com . recommended esd management refer to the application note an0020 available at http://www.ums - gaas.com for esd sensitivity and handling recommendations for the ums package products. ordering information qfn 28l 5x5 package: cha4220 - qgg /xy stick: xy = 20 tape & reel: xy = 21 information furnished is believed to be accurate and reliable. however united monolithic semiconductors s.a.s. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or pate nt rights of united monolithic semiconductors s.a.s. . specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. united monolithic semiconductors s.a.s. p roducts are not authorised for use as critical components in life support devices or systems without express written approval from united monolithic semiconductors s.a.s.

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